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EL5173, EL5373
Data Sheet February 4, 2008 FN7312.7
450MHz Differential Twisted-Pair Drivers
The EL5173 and EL5373 are single and triple high bandwidth amplifiers with a fixed gain of 2. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs can be in either single-ended or differential form but the outputs are always in differential form. The output common mode level for each channel is set by the associated REF pin, which have a -3dB bandwidth of over 190MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL5173 and EL5373 are specified for operation over the full -40C to +85C temperature range.
Features
* Fully differential inputs and outputs * Differential input range 2.3V * 450MHz 3dB bandwidth at fixed gain of 2 * 900V/s slew rate (EL5173) * 1100V/s slew rate (EL5373) * Single 5V or dual 5V supplies * 40mA maximum output current * Low power - 12mA per channel * Pb-free available (RoHS compliant)
Applications
* Twisted-pair drivers * Differential line drivers * VGA over twisted-pairs * ADSL/HDSL drivers
Pinouts
EL5173 (8 LD SOIC, MSOP) TOP VIEW
1 IN+ 2 EN 3 IN4 REF OUT 8 VS- 7 VS+ 6 OUTB 5 EN 1 INP1 2 INN1 3 REF1 4 NC 5 INP2 6 INN2 7 REF2 8 NC 9 INP3 10 INN3 11 REF3 12 + + -
EL5373 (24 LD QSOP) TOP VIEW
24 OUT1 23 OUT1B 22 NC 21 VSP 20 VSN 19 NC 18 OUT2 17 OUT2B 16 NC 15 OUT3 14 OUT3B 13 NC
+ -
* Single ended to differential amplification * Transmission of analog signals in a noisy environment
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5173, EL5373 Ordering Information
PART NUMBER EL5173IS EL5173IS-T7 EL5173IS-T13 EL5173ISZ (Note) EL5173ISZ-T7 (Note) EL5173ISZ-T13 (Note) EL5173IY EL5173IY-T7 EL5173IY-T13 EL5173IYZ (Note) EL5173IYZ-T7 (Note) EL5173IYZ-T13 (Note) EL5373IU EL5373IU-T7 EL5373IU-T13 EL5373IUZ (Note) EL5373IUZ-T7 (Note) EL5373IUZ-T13 (Note) 5173IS 5173IS 5173IS 5173ISZ 5173ISZ 5173ISZ i i i BAAYA BAAYA BAAYA EL5373IU EL5373IU EL5373IU EL5373IUZ EL5373IUZ EL5373IUZ PART MARKING 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) PACKAGE PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
* Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7312.7 February 4, 2008
EL5173, EL5373
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V Supply Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . 1V/s max. Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Thermal Information
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Recommended Operating Temperature . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW BW SR
VS+ = +5V, VS- = -5V, TA = +25C, VIN = 0V, RLD = 200, CLD = 1pF, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT
-3dB Bandwidth 0.1dB Bandwidth Slew Rate - EL5173 Slew Rate - EL5373 VOUT = 2VP-P, 20% to 80% VOUT = 2VP-P, 20% to 80% VOUT = 2VP-P VODP-P = 2V 750 900
450 60 900 1100 10 10 10 AV =1, CLD = 2.7pF VOUT = 2VP-P, 20% to 80% VOUT = 2VP-P, 20% to 80% f = 10kHz VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz RLD = 300, AV = 2 RLD = 300, AV = 2 at 1MHz 190 200 125 25 84 71 62 53 0.05 0.08 90
MHz MHz V/s V/s ns % ns MHz V/s V/s nV/Hz dBc dBc dBc dBc % dB
TSTL OS TOVR VREFBW (-3dB) VREFSR+ VREFSRVN HD2 HD2 HD3 HD3 dG d eS
Settling Time to 0.1% Overshoot Output Overdrive Recovery Time VREF -3dB Bandwidth VREF Slew Rate - Rise VREF Slew Rate - Fall Input Voltage Noise Second Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Third Harmonic Distortion Differential Gain at 3.58MHz Differential Phase at 3.58MHz Channel Separation - for EL5373 only
INPUT CHARACTERISTICS VOS IIN Input Referred Offset Voltage Input Bias Current (VIN, VINB) EL5173 EL5373 IREF INput Bias Current at REF VREF = +3.2V VREF = -3.2V Gain RIN CIN DMIR CMIR+ Gain Accuracy Differential Input Resistance Differential Input Capacitance Differential Mode Input Range Common Mode Positive Input Range at VIN+, VIN2 3.1 VIN = 1V -21 -21 1 -1 1.97 1.99 150 1 2.3 3.4 3 -11 -13 30 -5 -5 5 +1 2.01 mV A A A A V k pF V V
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FN7312.7 February 4, 2008
EL5173, EL5373
Electrical Specifications
PARAMETER CMIRVREFIN+ VREFINVREFOS CMRR VS+ = +5V, VS- = -5V, TA = +25C, VIN = 0V, RLD = 200, CLD = 1pF, Unless Otherwise Specified (Continued) DESCRIPTION Common Mode Negative Input Range at VIN+, VINReference Input - Positive Reference Input - Negative Output Offset Relative to VREF Input Common Mode Rejection Ratio VIN = 2.5V VIN+ = VIN- = 0V VIN+ = VIN- = 0V -100 60 3.3 CONDITIONS MIN TYP -4.5 3.7 -3.3 50 80 -3 +100 MAX -4.2 UNIT V V V mV dB
OUTPUT CHARACTERISTICS VOUT (EL5173) VOUT (EL5373) IOUT(Max) Positive Output Voltage Swing Negative Output Voltage Swing Positive Output Voltage Swing Negative Output Voltage Swing Maximum Output Current RL = 10 (EL5173) RL = 10 (EL5373) ROUT SUPPLY VSUPPLY IS(ON) Supply Operating Range Power Supply Current - Per Channel EN pin tied to 4.8V VS+ to VS4.75 9 60 -150 EN pin tied to 4.8V 0.5 -150 VS from 4.5V to 5.5V 60 12 80 -120 2 -120 73 11 14 100 -90 10 -90 V mA A A A A dB Output Impedance 45 40 RLD = 200 3.7 RLD = 200 3.3 3.67 -3.3 4 -3.7 55 50 60 -3.4 -3 V V V V mA mA m
IS(OFF)+ (EL5173) Positive Power Supply Current - Disabled IS(OFF)- (EL5173) Negative Power Supply Current - Disabled
IS(OFF)+ (EL5373) Positive Power Supply Current - Disabled IS(OFF)- (EL5373) PSRR ENABLE tEN tDS VIH VIL IIH-EN IIL-EN Enable Time Disable Time EN Pin Voltage for Power-Up EN Pin Voltage for Shut-Down EN Pin Input Current High - Per Channel EN Pin Input Current Low - Per Channel Negative Power Supply Current - Disabled Power Supply Rejection Ratio
100 1.2 VS+ - 1.5 VS+ - 0.5 At VEN = 5V At VEN = 0V -5 40 -2.5 60
ns s V V A A
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FN7312.7 February 4, 2008
EL5173, EL5373 Pin Descriptions
EL5173 PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME IN+ EN INREF OUTB VS+ VSOUT NC EL5373 PIN NUMBER 2, 6, 10 1 3, 7, 11 4, 8, 12 14, 17, 23 21 20 15, 18, 24 5, 9, 13, 16, 19, 22 PIN NAME INP1, 2, 3 EN INN1, 2, 3 REF1, 2, 3 OUT3B, 2B, 1B VS+, VSP VS-, VSN OUT3, 2, 1 NC Non-inverting inputs ENABLE Inverting inputs, note that on EL5173, this pin is also the REF pin Reference inputs, sets common-mode output voltage Inverting outputs Positive supply Negative supply Non-inverting outputs No connect; grounded for best crosstalk performance PIN FUNCTION
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FN7312.7 February 4, 2008
Connection Diagrams
EL5173
CL1 RS1 50 INP EN INN REF RS2 50 RS3 50 1 IN+ 2 EN 3 IN4 REF OUT 8 50 VS- 7 VS+ 6 RRT2 OUTB 5 +5V CL2 50 LOADN -5V RRT2 LOADP
6
ENABLE INP1 INN1 REF1 INP2 INN2 REF2 INP3 INN3 REF3 RSP1 50
FN7312.7 February 4, 2008
EL5373
+5V RRT1 1 EN 2 INP1 3 INN1 4 REF1 5 NC 6 INP2 7 INN2 8 REF2 9 NC 10 INP3 11 INN3 12 REF3 RSN1 50 RSR1 50 RSP2 50 RSN2 50 RSR2 50 RSP3 50 RSN3 50 RSR3 50 -5V OUT1 24 RRT1B OUT1B 23 50 NC 22 VSP 21 VSN 20 NC 19 RRT2 OUT2 18 RRT2B OUT2B 17 50 NC 16 RRT3 OUT3 15 RRT3B OUT3B 14 50 NC 13 50 LD3B LD3 50 LD2B LD2 50 LD1B LD1
EL5173, EL5373
EL5173, EL5373 Typical Performance Curves
VS = 5V, RLD = 200 10 9 8 7 GAIN (dB) 6 5 4 3 2 1 0 1M 10M 100M 1G VODP-P = 700mV VODP-P = 200mV 10 9 8 7 GAIN (dB) 6 5 4 3 2 1 0 100k 1M 10M FREQUENCY (Hz) 100M 1G RLD = 100 RLD = 200 RLD = 1k RLD = 500 VS = 5V, CLD = 1pF
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. FREQUENCY RESPONSE vs RLD
VS = 5V, RLD = 200, VODP-P = 200mV 11 10 9 8 GAIN (dB) 7 6 5 4 3 2 1 1M 10M 100M 1G CLD = 2.3pF CLD = 0pF CLD = 16pF CLD = 5pF GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M 1G VREF = 1VP-P VREF = 200mVP-P
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE vs CLD
FIGURE 4. FREQUENCY RESPONSE vs VREF
VINCM
100 + VODM 100 VOCM
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 100k 1M 10M 100M PSRR+ PSRRCOMMON MODE REJECTION (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 100k 1M VODM/VINCM 10M FREQUENCY (Hz) 100M 1G VOCM/VINCM
FREQUENCY (Hz)
FIGURE 5. PSRR vs FREQUENCY
FIGURE 6. COMMON MODE REJECTION vs FREQUENCY
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FN7312.7 February 4, 2008
EL5173, EL5373 Typical Performance Curves
VIN RT 100 + R
(Continued)
VODM 100
VOCM
0 -10 BALANCE ERROR (dB) -20 -30 -40 -50 -60 100k VOCM/VODM
1000 VOLTAGE NOISE (nV/Hz)
100
1M
10M FREQUENCY (Hz)
100M
1G
10 10
100
1k
10k
100k
1M
10M
FREQENCY (Hz)
FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE ERROR vs FREQUENCY
FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY
VODMP-P = 200mV, RLD = 200 -30 CHANNEL SEPARATION (dB) -40 -50 BW (MHz) -60 -70 -80 -90 -100 -110 100k 1M 10M FREQUENCY (Hz) CH3-->CH2 CH2-->CH1 CH2-->CH3 CH1-->CH2 CH3-->CH1 CH1-->CH3 100M 1G 460 440 420 400 380 360 340 320 300 4 5 6 7 VS (V) 8 9 10 11
FIGURE 9. CHANNEL SEPARATION vs FREQUENCY
FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE
11.9 11.8 DISTORTION (dB) IS+ 11.7 IS (mA) 11.6 11.5 11.4 11.3 4 IS-
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 5 6 7 VS (V) 8 9 10 11
VS = 5V, RLD = 200 HD3 (f=20MHz) HD3 (f=5MHz)
HD2 (f=20MHz) HD2 (f=5MHz)
1
2
3
4
5
6
7
8
9
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE
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FN7312.7 February 4, 2008
EL5173, EL5373 Typical Performance Curves
-40 -50 DISTORTION (dB) -60
HD3 (f
(Continued)
VS = 5V, VODMP-P = 2V
-40 -45 -50 DISTORTION (dB) -55 -60 -65 -70 -75 -80 -85 800 900 1000
VS = 5V, RLD = 200, VODMP-P = 2V
HD3 (f = 20MHz)
= 5M Hz
HD3
-70 -80 -90 -100 100
)
HD2
HD2 (f = 20MHz)
HD2 (f = 5MHz) 200 300 400 500 600 700
-90 0M
5M
10M
15M
20M
25M
30M
35M
40M
RLD ()
FREQUENCY (Hz)
FIGURE 13. HARMONIC DISTORTION vs RLD
FIGURE 14. HARMONIC DISTORTION vs FREQUENCY
100mV/DIV
0.5V/DIV
20ns/DIV
20ns/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
EMPTY BOARD
DISABLED OUT1B
OUT1
FIGURE 17. OUTPUT IMPEDANCE (DISABLED)
FIGURE 18. OUTPUT IMPEDANCE (ENABLED)
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FN7312.7 February 4, 2008
EL5173, EL5373 Typical Performance Curves
(Continued)
FIGURE 19. DISABLED RESPONSE
FIGURE 20. ENABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) MSOP8/10 JA = +115C/W 1.136W 909mW 870mW QSOP24 JA = +88C/W SO8 JA = +110C/W 1.2 1.0 0.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
870mW QSOP24 JA = +115C/W SO8 JA = +160C/W
625mW 0.6 0.4 486mW 0.2 0 0 25
MSOP8 JA = +206C/W 50 75 85 100 125 150
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7312.7 February 4, 2008
EL5173, EL5373 Simplified Schematic
200 VS+ R3 R1 R2 R7 R8 R4
IN+
IN-
FBP
FBN
VB1 OUT+ RCD REF RCD VB2 CC R5 VSR6 OUTR9 R10
CC
400
200
Description of Operation and Application Information
Product Description
The EL5173 and EL5373 are wide bandwidth, low power and single/differential ended to differential output amplifiers. They have a fixed gain of 2. The EL5173 is a single channel differential amplifier. The EL5373 is a triple channel differential amplifier. The EL5173 and EL5373 have a -3dB bandwidth of 450MHz while driving a 200 differential load. The EL5173 and EL5373 are available with a power down feature to reduce the power while the amplifiers are disabled.
Driving Capacitive Loads and Cables
The EL5173 and EL5373 can drive 16pF differential capacitor in parallel with 200 differential load with less than 3.5dB of peaking. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Input, Output and Supply Voltage Range
The EL5173 and EL5373 have been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.5V to 3.4V for 5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.7V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. The output of the EL5173 and EL5373 can swing from -3.3V to 3.6V at 200 differential load at 5V supply. As the load resistance becomes lower, the output swing is reduced.
Disable/Power-Down
The EL5173 and EL5373 can be disabled and placed their outputs in a high impedance state. The turn off time is about 1.2s and the turn on time is about 100ns. When disabled, the amplifier's supply current is reduced to 40A for IS+ and 2.5A for IS- typically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V.
Differential and Common Mode Gain Settings
As shown at the simplified schematic, since the feedback resistors RF and the gain resistor are integrated with 200 and 400, the EL5173 and EL5373 have a fixed gain of 2. The common mode gain is always one.
Output Drive Capability
The EL5173 and EL5373 have internal short circuit protection. Its typical short circuit current is 55mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed.
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FN7312.7 February 4, 2008
EL5173, EL5373
Maximum reliability is maintained if the output current never exceeds 60mA. This limit is set by the design of the internal metal interconnect. Where: * VS = Total supply voltage * ISMAX = Maximum quiescent supply current per channel * VO = Maximum differential output voltage of the application * RLD = Differential load resistance * ILOAD = Load current * i = Number of channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat.
Power Dissipation
With the high output drive capability of the EL5173 and EL5373 it is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 1)
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
Where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
V O PD = i x V S x I SMAX + V S x ----------- R LD (EQ. 2)
Typical Applications
Twisted pair cable driver
0
50 50 EL5173/ EL5373
VFB VIN EL5175/ EL5375
VOUT
50 ZO = 100 50
VINB VREF
FIGURE 23. TWISTED PAIR CABLE DRIVER
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FN7312.7 February 4, 2008
EL5173, EL5373 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL Au
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L
0.010
4x
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7312.7 February 4, 2008
EL5173, EL5373 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 4x DETAIL X
A1
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FN7312.7 February 4, 2008
EL5173, EL5373 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3x
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN7312.7 February 4, 2008

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Price & Availability of EL517308

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